Episode Details

"Mostly missless memory in the Mill CPU: Avoiding the pain of cache misses in a statically-scheduled architecture" -Ivan Godard, Out-of-the-Box Computing

Uploaded 24-10-13

Colloquium on Computer Systems Seminar Series (EE380) presents the current research in design, implementation, analysis, and use of computer systems. Topics range from integrated circuits to operating systems and programming languages. It is free and open to the public, with new lectures each week.

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0:00 Introduction
1:02 The Mill Architecture
3:37 Wide issue
5:02 Exposed pipeline
9:16 The memory hierarchy
11:10 The load problem
12:08 Every CPU's goal - hide load latency
13:20 Hardware approach - dynamic scheduling
22:18 Several different load problems...
24:36 Mill "deferred loads"
28:56 Deferred loads vs. alternatives
32:57 Reordering constraints
34:50 So eliminate aliasing
35:53 Alias immunity
37:09 Loads across control flow
38:14 Pickup loads
39:41 Compiler strategy
41:32 The trade-off
42:22 Implementation - the retire station
43:33 Implementation - stream monitoring
46:06 Retire station allocation
48:00 The fine print #1
50:33 The fine print #2
51:29 When stores miss...
52:45 Valid bits
58:50 Hierarchy from 40,000 ft.

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