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An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
Published 6 months, 2 weeks ago
Description
## Episode Summary
In this episode, we cover:
- **An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks** (arXiv)
- **TurboMem: High-Performance Lock-Free Memory Pool with Transparent Huge Page Auto-Merging for DPDK** (arXiv)
- **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch)
- **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com** (google_riscv)
- **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv)
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